1. Field of the Invention
Embodiments of the invention relate generally to non-volatile memory devices and, more specifically, to methods and apparatuses for determining a threshold voltage of a non-volatile memory cell.
2. State of the Art
Non-volatile semiconductor memories are becoming increasingly popular in a wide range of electronic applications from computer systems to personal appliances such as cellular phones, personal digital assistants, cameras, and music players. With the increased popularity comes an increased need for device speed and accuracy.
Non-volatile memory cells, such as Electrically Erasable Programmable Memories (EEPROMS)/Flash EEPROMS, and Flash memories, store information in a field effect transistor (FET) using a floating gate disposed between the substrate and a control gate. FIG. 1 illustrates a Flash cell comprising a conventional transistor used in Flash memories. The Flash cell 10 includes a drain 12, a source 14, the floating gate 16, and the control gate 18. The floating gate 16 is isolated from the control gate 18 and substrate by dielectric layers formed above and below the floating gate. In Flash memories, the control gates of a plurality of Flash cells are coupled to a word line. Thus, the signal on the control gate is referred to herein as Vw1, or variations thereof.
The term “threshold voltage” refers to the voltage required on the control gate 18 to cause the device to conduct between the source 14 and drain 12 regions. The charge on the floating gate 16 is dependent upon the number of electrons contained therein. The higher the number of electrons on the floating gate 16, the higher the voltage required on the control gate 18 for the cell to conduct. In other words, when the Flash cell 10 is programmed, electrons present on the floating gate 16 increase the threshold voltage required to enable the Flash cell current 22. When electrons are absent or removed, the threshold voltage required to enable cell current 22 is decreased. If the threshold voltage of a Flash cell 10 is above a certain level, the Flash cell 10 is considered to be in a programmed state, and if the threshold voltage is below the certain level, then the flash cell 10 is considered to be in an erased state. Thus, knowing the threshold voltage of a Flash cell 10 allows a determination of the state of the Flash cell 10 (programmed or erased) to be made.
FIG. 2 illustrates operational characteristics of a Flash cell as a current versus voltage curve. In operation, an erased Flash cell exhibits current characteristics as shown by curve 20, which is defined as a binary “1.” When the Flash cell is programmed, the additional charge on the floating gate moves the current curve for the Flash cell to a higher voltage. The more charge stored on the floating gate, the farther to the right the current curve will move. Curve 30 illustrates the current characteristics of a Flash cell safely programmed as a binary “0.” Curve 25 illustrates the current characteristics of a Flash cell that is at a minimum acceptable programming to be considered a “0.” Line 40 indicates a current threshold (Ith) at which a sense amplifier distinguishes between a programmed and an erased Flash cell. If a current from the Flash cell (Icell) is below Ith, the Flash cell will be considered erased, if Icell is above Ith, the Flash cell will be considered programmed. In other words, there is a threshold voltage (Vth), represented by line 50, at which the Flash cell conducts a high enough current for the sense amplifier to detect. Thus, after programming, a Flash cell may be read by applying a voltage that is midway between an erased voltage and a programmed voltage. With this voltage applied, if a current is sensed, the Flash cell is considered erased (i.e., “1” in this case). If a current is not sensed, the Flash cell is considered programmed (i.e., “0” in this case).
FIG. 3 is a circuit diagram of a portion of a conventional Flash memory device 100 configured as test logic for determining the cell current 116 of each cell 115 in NAND string 114. In general, FIG. 3 is used to depict a test configuration for a Flash memory device 100, rather than logic used during the normal functional operation of the Flash memory device 100. Each Flash cell 115 of NAND string 114 has a gate connected to a word line 118 from an X decoder 112. Vth PAD 122 is an input pad that may be used in a test mode configuration for driving an analog voltage at the desired Vth (i.e., threshold voltage). X decoder 112 decodes address signals (not shown) to activate the appropriate word line 118 of the selected Flash cell 114a by driving the word line 118 of the selected Flash cell 114a with the Vth signal from Vth PAD 122. Multiple sub-X decoders (one for each Flash cell) may be contained inside X decoder 112. For example, if NAND string 114 contains 32 cells, 32 sub-X decoders, for driving 32 word lines, may exist within X decoder 112. Bit line 124 is connected to the drain of NAND string 114, and the source of NAND string 114 is connected to ground potential VSS. Source select gate 134 allows the source of NAND string 114 to be selectively coupled to the ground potential VSS and drain select gate 132 allows the drain of NAND string 114 to be selectively coupled to the bit line 124. Generally, the gates of source select gate 134 and drain select gate 132 may be controlled by logic that operates during a normal functional configuration, whereas during a test mode configuration these gates may be configured with a signal that leaves the source select gate 134 and drain select gate 132 in an on configuration. Bit line 124 includes resistor 127, capacitor 129, and data_cache 125, which is a circuit used to control the read, program, and erase operations for each bit line 124. Resistor 127 and capacitor 129 are shown simply to illustrate the distributed capacitance and distributed resistance of bit line 124.
Cell current 116 flows from the drain to the source of selected Flash cell 114a and is measured during a test flow procedure. The test flow procedure requires a prolonged measurement process wherein a word line voltage is applied at a Flash cell and the current running through the cell is measured at Ith PAD 126. The word line voltage is varied and this procedure is repeated until a specific amount of current is flowing through the cell. This test flow measurement process can lead to long test times and eventually increased costs of production.
There is a need for methods and apparatuses that provides a means for determining a memory cell current internally, thus allowing the threshold voltage of the memory cell to be determined quickly and accurately in order to reduce the costs of production.